Abstract:
:State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25-50 more event transmission rate than other current neuromorphic communication infrastructures.
journal_name
Front Neuroscijournal_title
Frontiers in neuroscienceauthors
Scholze S,Schiefer S,Partzsch J,Hartmann S,Mayr CG,Höppner S,Eisenreich H,Henker S,Vogginger B,Schüffny Rdoi
10.3389/fnins.2011.00117subject
Has Abstractpub_date
2011-10-12 00:00:00pages
117eissn
1662-4548issn
1662-453Xjournal_volume
5pub_type
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